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hc05p1agrs/d rev. 3.0 non-disclosure agreement required MC68HC05P1A mc68hcl05p1a mc68hsc05p1a general release specification february 25, 1997 csic mcu design center austin, texas f r e e s c a l e s e m i c o n d u c t o r , i n c . . .
non-disclosure agreement required general release speci?cation MC68HC05P1A rev. 3.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification list of sections non-disclosure agreement required general release specification MC68HC05P1A list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 15 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 section 3. cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 section 6. operating modes. . . . . . . . . . . . . . . . . . . . . . 49 section 7. input/output ports . . . . . . . . . . . . . . . . . . . . . 55 section 8. 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 section 9. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . 77 section 10. electrical specifications . . . . . . . . . . . . . . . 95 section 11. mechanical specifications . . . . . . . . . . . . 107 section 12. ordering information . . . . . . . . . . . . . . . . . 109 appendix a. mc68hcl05p1a. . . . . . . . . . . . . . . . . . . . 113 appendix b. mc68hsc05p1a. . . . . . . . . . . . . . . . . . . . 119 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of sections general release specification MC68HC05P1A rev. 3.0 list of sections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification table of contents non-disclosure agreement required general release specification MC68HC05P1A table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.2 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.1 pa0Cpa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.2 pb5, pb6, and pb7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.3 pc0Cpc7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.4 pd5 and pd7/tcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.5 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.6.6 irq (maskable interrupt request) . . . . . . . . . . . . . . . . . . .24 section 2. memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 single-chip mode memory map . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 input/output (i/o) and control registers . . . . . . . . . . . . . . . . .25 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . .30 2.6 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . .30 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required table of contents general release specification MC68HC05P1A rev. 3.0 table of contents section 3. cpu core 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .34 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.3 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5.1 external interrupt ( irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5.2 optional external interrupts (pa0Cpa7) . . . . . . . . . . . . . . .42 4.5.3 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5.4 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.5.5 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.3 external reset ( reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2 computer operating properly (cop) reset . . . . . . . . . . . .46 section 6. operating modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents MC68HC05P1A rev. 3.0 general release specification table of contents non-disclosure agreement required 6.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.4.1.2 halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.4.2 wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.5 cop watchdog timer considerations . . . . . . . . . . . . . . . . . . .54 section 7. input/output ports 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 7.7 i/o port programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 section 8. 16-bit timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.3 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.4 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 8.5 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.8 timer operation during wait mode . . . . . . . . . . . . . . . . . . . . .75 8.9 timer operation during stop mode . . . . . . . . . . . . . . . . . . . . .75 section 9. instruction set 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required table of contents general release specification MC68HC05P1A rev. 3.0 table of contents 9.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . .82 9.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .83 9.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . .84 9.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . .86 9.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 9.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 section 10. electrical specifications 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 10.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 10.7 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . .98 10.8 3.3 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . .99 10.9 5.0 volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 10.10 3.3 volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 section 11. mechanical specifications 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.3 dual in-line package (case 710). . . . . . . . . . . . . . . . . . . . . .107 11.4 small outline integrated circuit (case 751f) . . . . . . . . . . . . .108 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
table of contents MC68HC05P1A rev. 3.0 general release specification table of contents non-disclosure agreement required section 12. ordering information 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .110 12.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . .112 12.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 appendix a. mc68hcl05p1a a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 a.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .114 a.4 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 appendix b. mc68hsc05p1a b.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 b.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .120 b.4 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 b.5 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required table of contents general release specification MC68HC05P1A rev. 3.0 table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification list of figures non-disclosure agreement required general release specification MC68HC05P1A list of figures figure title page 1-1 MC68HC05P1A block diagram . . . . . . . . . . . . . . . . . . . . . .17 1-2 single-chip pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1-3 low noise single-chip pinout . . . . . . . . . . . . . . . . . . . . . . .19 1-4 oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1-5 typical frequency versus resistance for rc oscillator mask option . . . . . . . . . . . . . . . . . . . . .22 2-1 single-chip mode memory map . . . . . . . . . . . . . . . . . . . . . .26 2-2 i/o and control registers $0000C$000f . . . . . . . . . . . . . . .27 2-3 i/o and control registers $0000C$000f . . . . . . . . . . . . . . .28 3-1 cpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3-2 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . .40 4-2 irq function block diagram . . . . . . . . . . . . . . . . . . . . . . . .41 5-1 reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5-2 cop watchdog timer location . . . . . . . . . . . . . . . . . . . . . .47 6-1 stop/halt/wait flowchart . . . . . . . . . . . . . . . . . . . . . . . .53 7-1 port a i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7-2 port b i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7-3 port c i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7-4 port d i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of figures general release specification MC68HC05P1A rev. 3.0 list of figures figure title page 8-1 16-bit timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . .64 8-2 timer registers (tmrh/tmrl) . . . . . . . . . . . . . . . . . . . . . .66 8-3 alternate counter registers (acrh/acrl) . . . . . . . . . . . . .66 8-4 state timing diagram for timer overflow . . . . . . . . . . . . . .67 8-5 state timing diagram for timer reset . . . . . . . . . . . . . . . . .67 8-6 output compare registers (ocrh/ocrl) . . . . . . . . . . . . .68 8-7 output compare software initialization example . . . . . . . . .70 8-8 state timing diagram for output compare . . . . . . . . . . . . .70 8-9 input compare registers (icrh/icrl) . . . . . . . . . . . . . . . .71 8-10 state timing diagram for input capture. . . . . . . . . . . . . . . .72 8-11 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . .73 8-12 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . .74 10-1 pa0Cpa7, pb5Cpb7, pc2Cpc5, pd5, and tcmp typical high-side driver characteristics . . . . . . . . . . . .100 10-2 pa0Cpa7, pc2Cpc5, pb0Cpb5, pd5, and tcmp typical low-side driver characteristics . . . . . . . . . . . .100 10-3 pc0Cpc1 typical high-side driver characteristics . . . . . .101 10-4 pc0Cpc1 typical low-side driver characteristics . . . . . .101 10-5 typical operating i dd (25 c). . . . . . . . . . . . . . . . . . . . . . .102 10-6 typical wait mode i dd (25 c) . . . . . . . . . . . . . . . . . . . . . .102 10-7 power-on reset and external reset timing diagram . . . .105 a-1 maximum run mode i dd versus internal clock frequency . . . . . . . . . . . . . . . . . . . . . . .116 a-2 maximum wait mode i dd versus internal clock frequency . . . . . . . . . . . . . . . . . . . . . . .116 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification list of tables non-disclosure agreement required general release specification MC68HC05P1A list of tables table title page 4-1 vector addresses for interrupts and reset . . . . . . . . . . . . . .38 6-1 operating mode conditions after reset. . . . . . . . . . . . . . . . .49 6-2 cop watchdog timer recommendations . . . . . . . . . . . . . . .54 7-1 port a i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 7-2 port b i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 7-3 port c i/o pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 7-4 port d i/o pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 9-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . .82 9-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . .83 9-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . .85 9-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . .86 9-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 9-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 a-1 low-power output voltage (v dd = 1.8C2.4 vdc) . . . . . . . . .114 a-2 low-power output voltage (v dd = 2.5C3.6 vdc) . . . . . . . . .114 a-3 low-power supply current. . . . . . . . . . . . . . . . . . . . . . . . . .115 a-4 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 b-1 high-speed supply current . . . . . . . . . . . . . . . . . . . . . . . . .120 b-2 high-speed control timing (v dd = 5.0 vdc 10%) . . . . . . .121 b-3 high-speed control timing (v dd = 3.3 vdc 10%) . . . . . . .121 b-4 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required list of tables general release specification MC68HC05P1A rev. 3.0 list of tables f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification general description non-disclosure agreement required general release specification MC68HC05P1A section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.2 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.1 pa0Cpa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.2 pb5, pb6, and pb7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.3 pc0Cpc7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.4 pd5 and pd7/tcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.6.5 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.6.6 irq (maskable interrupt request) . . . . . . . . . . . . . . . . . . .24 1.2 introduction the freescale MC68HC05P1A microcontroller unit (mcu) is pin compatible with the mc68hc05p1 with port and interrupt enhancements available. this device is available in a 28-pin dual in-line package (dip) or a small outline integrated circuit (soic) package. a functional block diagram of the MC68HC05P1A is shown in figure 1-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description general release specification MC68HC05P1A rev. 3.0 general description 1.3 features features of the MC68HC05P1A include: ? low-cost, m68hc05 core ? 28-pin dual in-line package (dip) or small outline integrated circuit (soic) package ? on-chip crystal/ceramic resonator or rc oscillator (mask option) ? 2320 bytes of user read-only memory (rom) including: C 48 bytes of page-zero rom C 16 bytes of user vectors ? 128 bytes of on-chip random access memory (ram) ? 16-bit timer with output compare and input capture ? edge/level-sensitive interrupt or edge-sensitive only (mask option) ? computer operating properly (cop) watchdog timer ? 20 bidirectional input/output (i/o) lines and one input-only line including: C individual mask selectable pullups/interrupts on port a pins C high current sink and source on two i/o pins (pc0 and pc1) ? single-chip mode ? power-saving stop and wait modes ? stop conversion to halt mode (mask option) note: a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. note: any reference to a voltage, current, or frequency specified in the following sections will refer to the nominal values. the exact values and their tolerance or limits are specified in section 10. electrical specifications . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description features MC68HC05P1A rev. 3.0 general release specification general description non-disclosure agreement required figure 1-1. MC68HC05P1A block diagram data direction register ph2 16-bit timer 1 input capture 1 output compare port d logic osc cond code reg index reg cpu control 0 0 0 stk pntr 1 1 0 0 0 0 0 ? 4 (27) osc 1 (26) osc 2 (25) pd7/tcap sram 128 bytes user rom 2320 bytes (24)tcmp (2) irq alu mc68hc05 cpu accum program counter cpu registers ? 2 *pa7 (3) *pa0 (10) *pa1 (9) *pa2 (8) *pa3 (7) *pa4 (6) *pa5 (5) *pa6 (4) port a (23) pd5 data direction register pc3 (19) pc4 (18) pc5 (17) pc6 (16) pc7 (15) pc2 (20) port c **pc1 (21) **pc0 (22) test rom 32 bytes (1) reset v dd (28) v ss (14) data direction register pb5 (11) pb6 (12) pb7 (13) port b cop * pullup/interrupt selectable via mask option ** high current source/sink capability power ( ) pin number 1 1 1 i n z c h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description general release specification MC68HC05P1A rev. 3.0 general description 1.4 mask options the MC68HC05P1A has 12 mask options. the default state of these mask options and their alternate states are: 1. irq is edge- and level-sensitive option for edge-sensitive only 2. crystal/ceramic resonator oscillator mode option for resistor/capacitor (rc) mode 3. cop watchdog timer enabled option to disable 4. stop instruction enabled option to convert to halt 5. eight (8) port a pullups/interrupts disabled option to individually enable 1.5 functional pin description the following paragraphs describe the functionality of each pin on the MC68HC05P1A package. the device also is available with an alternate pinout where v dd and v ss are adjacent to reduce radio frequency (rf) emissions. this also improves the ability to decouple v dd and v ss , which may provide some benefit for conducted rf emissions as well. the pinouts are shown in figure 1-2 and figure 1-3 . they are compatible with the mc68hc05p1 microcontroller unit (mcu). 1.5.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is connected to a regulated +5 volt supply and v ss is connected to ground. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, take special care to provide good power supply bypassing at the mcu. use bypass capacitors with good high-frequency characteristics, and position them as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description functional pin description MC68HC05P1A rev. 3.0 general release specification general description non-disclosure agreement required figure 1-2. single-chip pinout figure 1-3. low noise single-chip pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reset irq pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb5 pb6 pb7 v ss v dd osc1 osc2 pd7/tcap tcmp pd5 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reset irq pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb5 pb6 pb7 pc7 v dd osc1 osc2 pd7/tcap tcmp pd5 pc0 pc1 pc2 pc3 pc4 pc5 pc6 v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description general release specification MC68HC05P1A rev. 3.0 general description 1.5.2 osc1 and osc2 the osc1 and osc2 pins are the control connections for the on-chip oscillator. the osc1 and osc2 pins can accept: 1. a crystal, as shown in figure 1-4 (a) . 2. a ceramic resonator, as shown in figure 1-4 (a) . 3. an external resistor, as shown in figure 1-4 (b) . 4. an external clock signal, as shown in figure 1-4 (c) . figure 1-4. oscillator connections to v dd or stop to v dd or stop to v dd or stop (a) crystal or ceramic resonator connections (b) rc oscillator connections (c) external clock source connections osc1 osc2 mcu 27 pf 27 pf 4.7 m w mcu mcu osc1 osc2 r osc1 osc2 unconnected external clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description functional pin description MC68HC05P1A rev. 3.0 general release specification general description non-disclosure agreement required note: the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal ph2 bus clock operating frequency, f op . 1.5.2.1 crystal the circuit in figure 1-4 (a) shows a typical oscillator circuit for an at- cut, parallel resonant crystal. follow the crystal manufacturers recommendations, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. the load capacitance values used in the oscillator circuit design should include all stray capacitances. mount the crystal and components as closely as possible to the pins for startup stabilization and to minimize output distortion. 1.5.2.2 ceramic resonator in cost-sensitive applications, use a ceramic resonator in place of a crystal. use the circuit in figure 1-4 (a) for a ceramic resonator and follow the resonator manufacturers recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. mount the resonator and components as closely as possible to the pins for startup stabilization and to minimize output distortion. 1.5.2.3 rc oscillator the lowest cost oscillator uses the rc mask option and an external resistor. with this option, a resistor is connected to the oscillator pins, as shown in figure 1-4 (b) . the relationship between r and f op is shown in figure 1-5 . consult the factory for tolerance limits and design specifications. 1.5.2.4 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-4 (c) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description general release specification MC68HC05P1A rev. 3.0 general description figure 1-5. typical frequency versus resistance for rc oscillator mask option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general description reset MC68HC05P1A rev. 3.0 general release specification general description non-disclosure agreement required 1.6 reset driving this input low will reset the mcu to a known startup state. the reset pin contains an internal schmitt trigger to improve its noise immunity. refer to section 5. resets . 1.6.1 pa0Cpa7 these eight i/o pins comprise port a. the state of any pin is software programmable, and all port a lines are configured as inputs during power-on or reset. eight individual mask options can be chosen to enable pullups and interrupts (active low) on each port a pin. refer to section 4. interrupts and section 7. input/output ports . 1.6.2 pb5, pb6, and pb7 these three i/o pins comprise port b. the state of any pin is software programmable and all port b lines are configured as inputs during power-on or reset. refer to section 7. input/output ports . 1.6.3 pc0Cpc7 these eight i/o pins comprise port c. the state of any pin is software programmable and all port c lines are configured as inputs during power-on or reset. pc0 and pc1 are capable of sourcing and sinking more current than a typical i/o pin. refer to section 7. input/output ports and section 10. electrical specifications . 1.6.4 pd5 and pd7/tcap these two pins comprise port d and are shared with the 16-bit timer subsystem. the state of pd5 is software programmable and is configured as an input during power-on or reset. pd7 is always an input. it may be read at any time, regardless of the mode of operation of the 16-bit timer. refer to section 7. input/output ports and section 8. 16- bit timer . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general description general release specification MC68HC05P1A rev. 3.0 general description 1.6.5 tcmp this pin is the output from the 16-bit timers output compare function. it is low after reset. refer to section 8. 16-bit timer . 1.6.6 irq (maskable interrupt request) this input pin drives the asynchronous interrupt function of the mcu. the mcu will complete the current instruction being executed before it responds to the irq interrupt request. when irq is driven low, the event is latched internally to signify an interrupt has been requested. when the mcu completes its current instruction, the interrupt latch is tested. if the interrupt latch is set and the interrupt mask bit (i bit) in the condition code register is clear, the mcu will begin the interrupt sequence. depending on the mask option selected, the irq pin will trigger this interrupt on either a negative going edge at the irq pin and/or while the irq pin is held in the low state. in either case, the irq pin must be held low for at least one t ilih time period. the irq input requires an external resistor connected to v dd for wired-or operation. if the irq pin is not used, it must be tied to the v dd supply. the irq pin contains an internal schmitt trigger as part of its input circuitry to improve noise immunity. refer to section 4. interrupts . note: each of the port a i/o pins may be connected as an or function with the irq interrupt function by a mask option. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq pin. the edge or level sensitivity selected by a separate mask option for the irq pin also applies to the i/o pins ored to create the irq signal. note: if the voltage level applied to the irq pin exceeds 1.5 v dd , it may affect the mcus mode of operation. see section 6. operating modes . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification memory non-disclosure agreement required general release specification MC68HC05P1A section 2. memory 2.1 introduction 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 single-chip mode memory map . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 input/output (i/o) and control registers . . . . . . . . . . . . . . . . .25 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . .30 2.6 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.2 introduction the MC68HC05P1A utilizes 13 address lines to access an internal memory space covering 8 kbytes. this memory space is divided into i/o, ram, and rom areas. 2.3 single-chip mode memory map when the MC68HC05P1A is in the single-chip mode, the 32 bytes of i/o, 128 bytes of ram, 2256 bytes of user rom, 48 bytes of user page zero rom, 32 bytes of test rom, and 16 bytes of user vectors rom are all active, as shown in figure 2-1 . 2.4 input/output (i/o) and control registers figure 2-2 and figure 2-3 briefly describe the i/o and control registers at locations $0000C$001f. reading unimplemented bits will return unknown states, and writing unimplemented bits will be ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory general release specification MC68HC05P1A rev. 3.0 memory figure 2-1. single-chip mode memory map reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) timer vector (low byte) timer vector (high byte) reserved reserved $1ff6 $1ff7 $1ff8 $1ff9 $1ffa $1ffb $1ffc $1ffd $1ffe $1fff reserved $1ff5 reserved $1ff4 reserved $1ff3 reserved $1ff2 reserved $1ff1 $1ff0 $001f $0000 $0100 $00ff 0255 0256 stack 64 bytes internal ram 128 bytes i/o 32 bytes user vectors rom 16 bytes 8191 8176 8175 2304 2303 0192 0191 0080 0079 0032 0031 0000 $1fff $1ff0 $1fef $0900 $08ff $00c0 $00bf $0050 $004f $0020 $001f $0000 test rom 32 bytes unused 5632 bytes user rom 2048 bytes user rom 48 bytes i/o registers see figure 2-2 and figure 2-3 unused 48 bytes 0128 0127 $0080 $007f cop control user rom 208 bytes $1fd0 $1fcf 8144 8143 $1f00 $1eff 7936 7935 register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory input/output (i/o) and control registers MC68HC05P1A rev. 3.0 general release specification memory non-disclosure agreement required addr. register name bit 7 654321 bit 0 $0000 port a data (porta) read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: $0001 port b data (portb) read: pb7 pb6 pb5 00000 write: $0002 port c data (portc) read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: $0003 port d data (portd) read: pd7 0 pd5 10000 write: $0004 port a data direction (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: $0005 port b data direction (ddrb) read: ddrb7 ddrb6 ddrb5 11111 write: uuuuu $0006 port c data direction (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: $0007 port d data direction (ddrd) read: 0 0 ddrd5 00000 write: $0008 unimplemented read: write: $0009 unimplemented read: write: $000a unimplemented read: write: $000b unimplemented read: write: $000c unimplemented read: write: = unimplemented figure 2-2. i/o and control registers $0000C$000f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory general release specification MC68HC05P1A rev. 3.0 memory $000d unimplemented read: write: $000e unimplemented read: write: $000f unimplemented read: write: addr. register name bit 7 654321 bit 0 = unimplemented figure 2-2. i/o and control registers $0000C$000f (continued) addr. register name bit 7 654321 bit 0 $010d unimplemented read: write: $0011 unimplemented read: write: $0012 timer control register (tcr) read: icie ocie toie 000 iedg olvl write: $0013 timer status register (tsr) read: icf ocf tof 00000 write: $0014 input capture msb (icrh) read: icrh7 icrh6 icrh5 icrh4 icrh3 icrh2 icrh1 icrh0 write: $0015 input capture lsb (icrl) read: icrl7 icrl6 icrl5 icrl4 icrl3 icrl2 icrl1 icrl0 write: $0016 output compare msb (ocrh) read: ocrh7 ocrh6 ocrh5 ocrh4 ocrh3 ocrh2 ocrh1 ocrh0 write: = unimplemented r = reserved figure 2-3. i/o and control registers $010dC$001f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory input/output (i/o) and control registers MC68HC05P1A rev. 3.0 general release specification memory non-disclosure agreement required $0017 output compare msb (ocrl) read: ocrl7 ocrl6 ocrl5 ocrl4 ocrl3 ocrl2 ocrl1 ocrl0 write: $0018 timer msb (timrh) read: tmrh7 tmrh6 tmrh5 tmrh4 tmrh3 tmrh2 tmrh1 tmrh0 write: $0019 timer lsb (tmrl) read: tmrl7 tmrl6 tmrl5 tmrl4 tmrl3 tmrl2 tmrl1 tmrl0 write: $001a alternate counter msb (acrh) read: acrh7 acrh6 acrh5 acrh4 acrh3 acrh2 acrh1 acrh0 write: $001b alternate counter lsb (acrl) read: acrl7 acrl6 acrl5 acrl4 acrl3 acrl2 acrl1 acrl0 write: $001c unimplemented read: write: $001d unimplemented read: write: $001e unimplemented read: write: $001f reserved read: rrrrrrrr write: addr. register name bit 7 654321 bit 0 = unimplemented r = reserved figure 2-3. i/o and control registers $010dC$001f (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required memory general release specification MC68HC05P1A rev. 3.0 memory 2.5 random-access memory (ram) the user ram consists of 128 bytes (including the stack) at locations $0080C$00ff. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram from $00ff to $00c0. note: using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 2.6 read-only memory (rom) there are 2256 bytes of user rom at locations $0100C$08ff and $1f00C$1fcf, with 48 bytes in user page zero locations $0020C$004f, and 16 additional bytes for user vectors at locations $1ff0C$1fff. the test rom and test rom vectors are at locations $1fd0C$1fef. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification cpu core non-disclosure agreement required general release specification MC68HC05P1A section 3. cpu core 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.2 introduction this section describes the registers of the m68hc05 central processor unit (cpu). the stop and wait modes, initiated by software instructions, are also described here. 3.3 cpu registers the cpu contains the following registers: ? accumulator (a) ? index register (x) ? stack pointer (sp) ? program counter (pc) ? condition code register (ccr) these registers are hard-wired within the cpu and are not part of the memory map. figure 3-1 is a block diagram of the m68hc05 cpu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required cpu core general release specification MC68HC05P1A rev. 3.0 cpu core figure 3-1. cpu block diagram figure 3-2 shows the five cpu registers. figure 3-2. programming model cpu control arithmetic logic unit (alu) 0 0 0 0 1 1 z 1 1 1 h i n stack pointer program counter 0 0 0 accumulator index register c 0 condition code register cpu registers m68hc05 cpu stack pointer 0 0 0 0 1 1 z 1 1 1 h i n 0 0 0 c 0 condition code register 7 0 7 0 index register accumulator 12 7 5 0 a x sp pc ccr 15 12 0 program counter 743210 carry/borrow bit zero bit negative bit interrupt mask half-carry bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core cpu registers MC68HC05P1A rev. 3.0 general release specification cpu core non-disclosure agreement required 3.3.1 accumulator the accumulator (a) is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.3.2 index register the index register (x) is an 8-bit register used for the indexed addressing value to create an effective address. the index register also may be used as a temporary storage area. in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu finds the operand address by adding the index register contents to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu finds the operand address by adding the index register contents to a 16-bit immediate value. 3.3.3 stack pointer the stack pointer (sp) contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the eight most significant bits (msb) are permanently set to 00000011. these eight bits are appended to the six least significant bits (lsb) to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around 70 a 70 x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required cpu core general release specification MC68HC05P1A rev. 3.0 cpu core and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.3.4 program counter the program counter (pc) is a 13-bit register that contains the address of the next byte to be fetched. because addresses are often 16-bit values, the program counter may be thought of as having three additional upper bits that are always zeros. normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.3.5 condition code register the condition code register (ccr) is a 5-bit register in which the h, n, z, and c bits are used to indicate the results of the instruction just executed, and the i bit is used to enable or disable interrupts. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. consider the condition code register as having three additional upper bits that are always ones. h half carry this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. 12 7 50 0000011 sp 15 12 0 000 pc 743210 111hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
cpu core cpu registers MC68HC05P1A rev. 3.0 general release specification cpu core non-disclosure agreement required i interrupt when this bit is set, the timer and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the i bit is cleared. n negative when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. z zero when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. c carry/borrow when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required cpu core general release specification MC68HC05P1A rev. 3.0 cpu core f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification interrupts non-disclosure agreement required general release specification MC68HC05P1A section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.3 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5.1 external interrupt ( irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.5.2 optional external interrupts (pa0Cpa7) . . . . . . . . . . . . . . .42 4.5.3 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.5.4 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.5.5 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.2 introduction the mcu can be interrupted by: 1. non-maskable software interrupt instruction (swi) 2. external asynchronous interrupt ( irq) 3. optional external asynchronous interrupt on each port a pin ( irq, enabled by pullup mask option) 4. input capture interrupt (timer) 5. output compare interrupt (timer) 6. timer overflow interrupt (timer) interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is completed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts general release specification MC68HC05P1A rev. 3.0 interrupts when the current instruction is completed, the processor checks all pending hardware interrupts. if interrupts are not masked by the i bit being clear in the condition code register (ccr) and the corresponding interrupt enable bit being set, the processor proceeds with interrupt processing. otherwise, the next instruction is fetched and executed. the swi is executed the same as any other instruction, regardless of the state of the i bit. when an interrupt is processed, the cpu puts the register contents on the stack, sets the i bit in the ccr, and fetches the address of the corresponding interrupt service routine from the vector table at locations $1ff0C$1fff. if more than one interrupt is pending when the interrupt vector is fetched, the interrupt with the highest vector location, shown in table 4-1 , will be serviced first. an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the cpu state to be recovered from the stack and normal processing to resume at the next instruction that was executed when the interrupt took place. figure 4-1 shows the event sequence that occurs during interrupt processing. table 4-1. vector addresses for interrupts and reset register flag name enable bit interrupt cpu interrupt vector address n/a n/a n/a reset reset $1ffeC$1fff n/a n/a n/a software swi $1ffcC$1ffd n/a n/a n/a external interrupt irq $1ffaC$1ffb tsr icf icie timer input capture timer $1ff8C$1ff9 tsr ocf ocie timer output compare timer $1ff8C$1ff9 tsr tof toie timer over?ow timer $1ff8C$1ff9 n/a n/a n/a unimplemented n/a $1ff6-$1ff7 n/a n/a n/a unimplemented n/a $1ff4-$1ff5 n/a n/a n/a unimplemented n/a $1ff2-$1ff3 n/a n/a n/a unimplemented n/a $1ff0-$1ff1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts reset interrupt sequence MC68HC05P1A rev. 3.0 general release specification interrupts non-disclosure agreement required 4.3 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner, as shown in figure 4-1 . a low level input on the reset pin or internally generated rst signal causes the program to vector to its starting address, which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register is also set. the mcu is configured to a known state during a reset, as described in section 5. resets . 4.4 software interrupt (swi) the swi is an executable instruction. it is also a non-maskable interrupt since it is executed regardless of the state of the i bit in the ccr. as with any instruction, interrupts pending during the previous instruction will be serviced before the swi opcode is fetched. the interrupt service routine address for the swi instruction is specified by the contents of memory locations $1ffc and $1ffd. 4.5 hardware interrupts all hardware interrupts are maskable by the i bit in the ccr. if the i bit is set, all hardware interrupts (internal and external) are disabled. clearing the i bit enables the hardware interrupts. the hardware interrupts are explained in the following sections. 4.5.1 external interrupt ( irq) the irq pin drives an asynchronous interrupt to the cpu. an edge detector flip-flop is latched on the falling edge of irq. if either the output from the internal edge detector flip-flops or the level on the irq pin is low, a request is synchronized to the cpu to generate the irq interrupt. if the edge-sensitive only mask option is selected, the output of the internal edge detector flip-flop is sampled and the input level on the irq pin is ignored. the interrupt service routine address is specified by the contents of memory locations $1ffa and $1ffb. a block diagram of the irq function is shown in figure 4-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts general release specification MC68HC05P1A rev. 3.0 interrupts figure 4-1. interrupt processing flowchart note: the internal interrupt latch is cleared nine ph2 clock cycles after the interrupt is recognized (after location $1ffa is read). therefore, another external interrupt pulse can be latched during the irq service routine. is i bit set? from reset load pc from: swi: $1ffc, $1ffd irq: $1ffa-$1ffb timer: $1ff8-$1ff9 set i bit in ccr stack pc, x, a, cc clear irq request latch restore registers from stack cc, a, x, pc y n execute instruction fetch next instruction irq interrupt? y n timer interrupt? y n swi instruction? y n rti instruction? y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts hardware interrupts MC68HC05P1A rev. 3.0 general release specification interrupts non-disclosure agreement required figure 4-2. irq function block diagram note: when the edge- and level-sensitive mask option is selected, the voltage applied to the irq pin must return to the high state before the rti instruction in the interrupt service routine is executed to avoid the processor re-entering the irq service routine. the irq pin is one source of an irq interrupt, and a mask option can also enable the port a pins (pa0Cpa7) to act as other irq interrupt sources. these sources are all combined into a single oring function to be latched by the irq latch. any enabled irq interrupt source sets the irq latch on the falling edge of the irq pin or a port a pin if port a interrupts have been enabled. if edge-only sensitivity is chosen by a mask option, only the irq latch output can activate a request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: 1. falling edge on the irq pin with all enabled port a interrupt pins at a high level. 2. falling edge on any enabled port a interrupt pin with all other enabled port a interrupt pins and the irq pin at a high level. irq latch r v dd irq pin mask option (irq level) to irq processing in cpu to bih & bil instruction sensing rst irq vector fetch pa7 ddra7 pa0 ddra 0 pa0 irq inhibit (mask option) pa7 irq inhibit (mask option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts general release specification MC68HC05P1A rev. 3.0 interrupts if level sensitivity is chosen, the active high state of the irq input can also activate an irq request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: 1. low level on the irq pin. 2. falling edge on the irq pin with all enabled port a interrupt pins at a high level. 3. low level on any enabled port a interrupt pin. 4. falling edge on any enabled port a interrupt pin with all enabled port a interrupt pins on the irq pin at a high level. this interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1ffa and $1ffb. the irq latch is automatically cleared by entering the interrupt service routine. 4.5.2 optional external interrupts (pa0Cpa7) the irq interrupt can be triggered by the inputs on the pa0Cpa7 port pins if enabled by individual mask options. with pullup enabled, each port a pin can activate the irq interrupt function and the interrupt operation will be the same as for inputs to the irq pin. once enabled by mask option, each individual port a pin can be disabled as an interrupt source if its corresponding ddr bit is configured for output mode. note: the bih and bil instructions apply to the output of the logic or function of the enabled pa0Cpa7 interrupt pins and the irq pin. the bih and bil instructions do not exclusively test the state of the irq pin. note: if enabled, the pa0Cpa7 pins will cause an irq interrupt only if these individual pins are configured as inputs. 4.5.3 input capture interrupt the input capture interrupt is generated by the 16-bit timer as described in section 8. 16-bit timer . the input capture interrupt flag is located in register tsr and its corresponding enable bit can be found in register tcr. the i bit in the ccr must be clear for the input capture interrupt to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
interrupts hardware interrupts MC68HC05P1A rev. 3.0 general release specification interrupts non-disclosure agreement required be enabled. the interrupt service routine address is specified by the contents of memory locations $1ff8 and $1ff9. 4.5.4 output compare interrupt the output compare interrupt is generated by the 16-bit timer as described in section 8. 16-bit timer . the output compare interrupt flag is located in register tsr and its corresponding enable bit can be found in register tcr. the i bit in the ccr must be clear for the output compare interrupt to be enabled. the interrupt service routine address is specified by the contents of memory locations $1ff8 and $1ff9. 4.5.5 timer overflow interrupt the timer overflow interrupt is generated by the 16-bit timer as described in section 8. 16-bit timer . the timer overflow interrupt flag is located in register tsr and its corresponding enable bit can be found in register tcr. the i bit in the ccr must be clear for the timer overflow interrupt to be enabled. this internal interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1ff8 and $1ff9. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required interrupts general release specification MC68HC05P1A rev. 3.0 interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification resets non-disclosure agreement required general release specification MC68HC05P1A section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.3 external reset ( reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.2 computer operating properly (cop) reset . . . . . . . . . . . .46 5.2 introduction the mcu can be reset from three sources: one external input and two internal reset conditions. the reset pin is an input with a schmitt trigger, as shown in figure 5-1 . the cpu and all peripheral modules will be reset by the rst signal, which is the logical or of internal reset functions and is clocked by ph2. figure 5-1. reset block diagram reset rst power-on reset (por) reset cop watchdog (copr) v dd osc data address latch to cpu and peripherals ph2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required resets general release specification MC68HC05P1A rev. 3.0 resets 5.3 external reset ( reset) the reset input is the only external reset and is connected to an internal schmitt trigger. the external reset occurs whenever the reset input is driven below the lower threshold and remains in reset until the reset pin rises above the upper threshold. the upper and lower thresholds are given in section 10. electrical specifications . 5.4 internal resets the two internally generated resets are the initial power-on reset (por) function and the cop watchdog timer function. 5.4.1 power-on reset (por) the internal por is generated at power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 ph2 clock cycle oscillator stabilization delay after the oscillator becomes active. 5.4.2 computer operating properly (cop) reset when the cop watchdog timer is enabled (by mask option), the internal cop reset is generated automatically by a timeout of the cop watchdog timer. this timer is implemented with an 18-stage ripple counter that provides a timeout period of 65.5 ms when a 4-mhz oscillator is used. the cop watchdog counter is cleared by writing a logic 0 to bit zero at location $1ff0. the cop watchdog timer can be disabled by mask option or by applying 2 v dd to the irq pin. when the irq pin is returned to its normal operating voltage range (between v ss and v dd ), the cop watchdog timer output will be restored if the cop mask option is enabled. the cop register is shared with the most significant bit (msb) of an unimplemented user interrupt vector as shown in figure 5-2 . reading f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
resets internal resets MC68HC05P1A rev. 3.0 general release specification resets non-disclosure agreement required this location returns the msb of the unimplemented user interrupt vector. writing a logic 0 to this location clears the cop watchdog timer. addr. register name bit 7 654321 bit 0 $1ff0 unimplemented vector and cop watchdog timer read: rrrrrrr r write: copc r = reserved figure 5-2. cop watchdog timer location f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required resets general release specification MC68HC05P1A rev. 3.0 resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification operating modes non-disclosure agreement required general release specification MC68HC05P1A section 6. operating modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.4.1.2 halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.4.2 wait instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.5 cop watchdog timer considerations . . . . . . . . . . . . . . . . . . .54 6.2 introduction the MC68HC05P1A uses single-chip mode. the conditions required to enter this mode are shown in table 6-1 . the mode of operation is determined by the voltages on the irq and pd7/tcap pins on the rising edge of the external reset pin. the mode of operation is also determined whenever the internal cop watchdog timer resets the mcu. when the cop timer expires, the voltage applied to the irq pin affects the mode of operation, while the voltage applied to pd7/tcap is ignored if the voltage at the irq pin table 6-1. operating mode conditions after reset reset pin irq pin pd7/tcap mode v ss to v dd v ss to v dd single-chip v tst = 2 x v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes general release specification MC68HC05P1A rev. 3.0 operating modes exceeds v tst . in this case, the voltage applied to pd7/tcap during the last rising edge on reset is stored in a latch and used to determine the mode of operation when the cop watchdog timer resets the mcu. 6.3 single-chip mode the single-chip mode allows the mcu to function as a self-contained microcontroller with maximum use of the pins for on-chip peripheral functions. all address and data activity occurs within the mcu and is not available externally. single-chip mode is entered on the rising edge of reset if the irq pin is within the normal operating voltage range. the pinout for the single-chip mode is shown in figure 1-2 . single-chip pinout . in the single-chip mode, two 8-bit i/o ports, one 3-bit i/o port, and a 1-bit i/o port are shared with the 16-bit timer subsystem. the 16-bit timer subsystem also has one input-only pin and one output-only pin. 6.4 low-power modes the MC68HC05P1A is capable of running in a low-power mode in each of its configurations. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. the stop conversion mask option is used to modify the behavior of the stop instruction from stop mode to halt mode. the flow of the stop, halt, and wait modes is shown in figure 6-1 . 6.5 stop instruction the stop instruction can result in one of two modes of operation, depending on the stop conversion mask option. if the stop conversion is not chosen, the stop instruction will behave like a normal stop instruction in the m68hc05 family and place the mcu in the stop mode. if the stop conversion is chosen, the stop instruction will behave like a wait instruction (with the exception of a variable delay at startup) and place the mcu in halt mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes stop instruction MC68HC05P1A rev. 3.0 general release specification operating modes non-disclosure agreement required 6.5.0.1 stop mode execution of the stop instruction without conversion to halt places the mcu in its lowest-power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. execution of the stop instruction automatically clears the i bit in the condition code register so that the external interrupt is enabled. all other registers and memory remain unaltered. all input/output lines remain unchanged. the mcu can be brought out of stop mode only by an external interrupt or an externally generated reset. when exiting the stop mode, the internal oscillator will resume after a 4064 ph2 clock cycle oscillator stabilization delay. note: execution of the stop instruction without conversion to halt (via mask option) will cause the oscillator to stop, and therefore disable the cop watchdog timer. if the cop watchdog timer is used, the stop mode should be changed to halt mode by selecting the appropriate mask option. 6.5.0.2 halt mode execution of the stop instruction with the conversion to halt places the mcu in this low-power mode. halt mode consumes the same amount of power as wait mode. (both halt and wait modes consume more power than stop mode.) in halt mode, the ph2 clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated from the cop watchdog timer. execution of the stop instruction automatically clears the i bit in the condition code register, enabling the external interrupt. all other registers, memory, and input/output lines remain in their previous states. if the 16-bit timer interrupt is enabled, the processor will exit halt mode and resume normal operation. halt mode also can be exited when an external interrupt or external reset occurs. when exiting the halt mode, the ph2 clock will resume after a delay of one to 4064 ph2 clock cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes general release specification MC68HC05P1A rev. 3.0 operating modes this varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of stop mode), which has been free-running (a feature of wait mode). note: halt mode is not intended for normal use. this feature is provided to keep the cop watchdog timer active in the event a stop instruction is inadvertently executed. 6.5.1 wait instruction the wait instruction places the mcu in a low-power mode, which consumes more power than stop mode. in wait mode, the ph2 clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the 16- bit timer and reset to be generated from the cop watchdog timer. execution of the wait instruction automatically clears the i bit in the condition code register, enabling the external interrupt. all other registers, memory, and input/output lines remain in their previous state. if the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal operation. the 16-bit timer may be used to generate a periodic exit from the wait mode. wait mode may also be exited when an external interrupt or reset occurs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
operating modes stop instruction MC68HC05P1A rev. 3.0 general release specification operating modes non-disclosure agreement required figure 6-1. stop/halt/wait flowchart 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine wait stop to halt mask option? y n external reset? y n external interrupt ? y n stop external oscillator, stop internal timer clock, reset startup delay restart external oscillator, restart stabilization delay stop internal processor clock, clear i-bit in ccr end of stabilization delay? y n y n external oscillator active and internal timer clock active restart internal processor clock stop internal processor clock, clear i-bit in ccr timer internal interrupt? y n external reset? y n stop halt external reset? y n y n stop internal processor clock, clear i-bit in ccr external oscillator active and internal timer clock active timer internal interrupt ? y n cop internal reset? y n cop internal reset? y n external interrupt ? external interrupt ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required operating modes general release specification MC68HC05P1A rev. 3.0 operating modes 6.6 cop watchdog timer considerations the cop watchdog timer is active in single-chip mode of operation when selected by mask option. executing the stop instruction without conversion to halt (via mask option) will cause the cop to be disabled. therefore, it is recommended that the stop instruction be modified to produce halt mode (via mask option) if the cop watchdog timer will be enabled. furthermore, it is recommended that the cop watchdog timer be disabled for applications that will use the halt or wait modes for time periods that will exceed the cop timeout period. cop watchdog timer interactions are summarized in table 6-2 . table 6-2. cop watchdog timer recommendations if the following condition exists: then the cop watchdog timer should be: stop instruction modes wait period halt mode selected via mask option wait period less than cop timeout enable or disable cop via mask option halt mode selected via mask option wait period more than cop timeout disable cop via mask option stop mode selected via mask option any length wait period disable cop via mask option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification input/output ports non-disclosure agreement required general release specification MC68HC05P1A section 7. input/output ports 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 7.7 i/o port programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 7.2 introduction in the single-chip mode, 20 bidirectional input/output (i/o) lines are arranged as two 8-bit i/o ports (ports a and c), one 3-bit i/o port (port b), and one 1-bit i/o port (port d). these ports are programmable as either inputs or outputs under software control of the data direction registers (ddrs). an input-only pin is associated with port d. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports general release specification MC68HC05P1A rev. 3.0 input/output ports 7.3 port a port a is an 8-bit bidirectional port, which can share its pins with the interrupt system as shown in figure 7-1 . each port a pin is controlled by the corresponding bits in a data direction register and a data register. the port a data register is located at address $0000. the port a data direction register (ddra) is located at address $0004. reset clears the ddra, thereby initializing port a as an input port. the port a data register is unaffected by reset. figure 7-1. port a i/o circuitry pullup read $0000 write $0000 read $0004 data register bit to interrupt system i/o pin output mask option (pullup inhibit) internal hc05 data bus reset (rst) write $0004 data direction register bit v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports port b MC68HC05P1A rev. 3.0 general release specification input/output ports non-disclosure agreement required 7.4 port b port b is a 3-bit bidirectional port that does not share any of its pins with other subsystems. the port b data register is located at address $0001 and its data direction register (ddr) is located at address $0005. reset does not affect the data registers but clears the ddrs, thereby setting all of the port pins to input mode. writing a 1 to a ddr bit sets the corresponding port pin to output mode (see figure 7-2 ). figure 7-2. port b i/o circuitry read $0001 write $0001 read $0005 data register bit i/o pin output internal hc05 data bus reset (rst) write $0005 data direction register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports general release specification MC68HC05P1A rev. 3.0 input/output ports 7.5 port c port c is an 8-bit bidirectional port that does not share any of its pins with other subsystems. the port c data register is located at address $0002, and its data direction register (ddr) is located at address $0006. reset does not affect the data registers but clears the ddrs, thereby setting all of the port pins to input mode. writing a 1 to a ddr bit sets the corresponding port pin to output mode (see figure 7-3 ). two port c pins, pc0 and pc1, can source and sink a higher current than a typical i/o pin. see section 10. electrical specifications regarding current specifications. figure 7-3. port c i/o circuitry read $0002 write $0002 read $0006 data register bit i/o pin output i nternal hc05 data bus reset (rst) write $0006 data direction register bit high current capability, pc0 and pc1 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports port d MC68HC05P1A rev. 3.0 general release specification input/output ports non-disclosure agreement required 7.6 port d port d is a 2-bit port with one bidirectional pin (pd5) and one input-only pin (pd7). pin pd7 is shared with the 16-bit timer. the port d data register is located at address $0003 and its data direction register (ddr) is located at address $0007. reset does not affect the data registers but clears the ddrs, thereby setting pd5 to input mode. writing a 1 to ddr bit 5 sets pd5 to output mode (see figure 7-4 ). port d may be used for general i/o applications regardless of the state of the 16-bit timer. since pd7 is an input-only line, its state can be read from the port d data register at any time. figure 7-4. port d i/o circuitry read $0003 write $0003 read $0007 data register bit i/o pin output internal hc05 data bus reset (rst) write $0007 data direction register bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports general release specification MC68HC05P1A rev. 3.0 input/output ports 7.7 i/o port programming each pin on ports a through d (except pin 7 of port d) may be programmed as an input or an output under software control as shown in table 7-1 , table 7-2 , table 7-3 , and table 7-4 . the direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (ddr). a pin is configured as an output if its corresponding ddr bit is set to a logic 1. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. table 7-1. port a i/o pin functions ddra i/o pin mode accesses to ddra @ $0004 accesses to data register @ $0000 irq source read/write read write 0 input, hi-z ddra0Cddra7 i/o pin * enabled** 1 output ddra0Cddra7 pa0Cpa7 pa0Cpa7 disabled *does not affect input, but stored to data register **if enabled via mask option table 7-2. port b i/o pin functions ddrb i/o pin mode accesses to ddrb @ $0005 accesses to data register @ $0001 read/write read write 0 input, hi-z ddrb5Cddrb7 i/o pin * 1 output ddrb0Cddrb7 pb5Cpb7 pb5Cpb7 *does not affect input, but stored to data register table 7-3. port c i/o pin functions ddrc i/o pin mode accesses to ddrc @ $0006 accesses to data register @ $0002 read/write read write 0 input, hi-z ddrc0Cddra7 i/o pin * 1 output ddrc0Cddra7 pc0Cpc7 pc0Cpc7 *does not affect input, but stored to data register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
input/output ports i/o port programming MC68HC05P1A rev. 3.0 general release specification input/output ports non-disclosure agreement required note: to avoid generating a glitch on an i/o port pin, data should be written to the i/o port data register before writing a logical 1 to the corresponding data direction register. at power-on or reset, all ddrs are cleared, which configures all port pins as inputs. the ddrs are capable of being written to or read by the processor. during the programmed output state, a read of the data register will actually read the value of the output data latch and not the level on the i/o port pin. table 7-4. port d i/o pin functions ddrd i/o pin mode accesses to ddrd @ $0007 accesses to data register @ $0003 read/write read write 0 input, hi-z ddrd5 i/o pin * 1 output ddrd5 pd5 pd5 *does not affect input, but stored to data register, pd7 is input-only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required input/output ports general release specification MC68HC05P1A rev. 3.0 input/output ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required general release specification MC68HC05P1A section 8. 16-bit timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.3 timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 8.4 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 8.5 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.6 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8.7 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 8.8 timer operation during wait mode . . . . . . . . . . . . . . . . . . . . .75 8.9 timer operation during stop mode . . . . . . . . . . . . . . . . . . . . .75 8.2 introduction the MC68HC05P1A mcu contains a single 16-bit programmable timer with an input capture function and an output compare function. the 16- bit timer is driven by the output of a fixed divide-by-four prescaler operating from the ph2 clock. the 16-bit timer may be used for many applications, including input waveform measurement, while simultaneously generating an output waveform. pulse widths can vary from microseconds to seconds depending on the oscillator frequency selected. the 16-bit timer also is capable of generating periodic interrupts. see figure 8-1 . because the timer has a 16-bit architecture, each function is represented by two registers. each register pair contains the high and low byte of that function. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer figure 8-1. 16-bit timer block diagram edge detector compare detector overflow detector ph2 clock free- running counter internal hc05 bus timer status register output compare ocrh ocrl input capture icrh icrl ocf tcap ? 4 buffer tmrh /acrh tmrl /acr l tof icf ocie toie icie olvl iedg timer control register interrupt generator r tcmp d > q reset timer interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required note: the i bit in the condition code register (ccr) should be set while manipulating both the high and low byte registers of a specific timer function. this prevents interrupts from occurring between the time that the high and low bytes are accessed. 8.3 timer the key element of the programmable timer is a 16-bit free-running counter, or timer registers, preceded by a prescaler, which divides the ph2 clock by four. the prescaler gives the timer a resolution of 2.0 microseconds when a 4-mhz crystal is used. the counter is incremented to increasing values during the low portion of the ph2 clock cycle. the double-byte, free-running counter can be read from either of two locations: the timer registers (tmrh and tmrl) or the alternate counter registers (acrh and acrl). both locations will contain identical values. a read sequence containing only a read of the least significant bit (lsb) of the counter (tmrl/acrl) will return the count value at the time of the read. if a read of the counter accesses the most significant bit (msb) first (tmrh/acrh), it causes the lsb (tmrl/acrl) to be transferred to a buffer. this buffer value remains fixed after the first msb byte read even if the msb is read several times. the buffer is accessed when reading the counter lsb (tmrl/acrl), and thus completes a read sequence of the total counter value. when reading either the timer or alternate counter registers, if the msb is read, the lsb must also be read to complete the read sequence. see figure 8-2 and figure 8-3 . the timer registers and alternate counter registers can be read at any time without affecting their value. however, the alternate counter registers differ from the timer registers in one respect: a read of the timer register msb can clear the timer overflow flag (tof). therefore, the alternate counter registers can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. see figure 8-4 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer tmrh $0018 bit 7 654321 bit 0 read: tmrh7 tmrh6 tmrh5 tmrh4 tmrh3 tmrh2 tmrh1 tmrh0 write: reset: 11111111 = unimplemented tmrl $0019 bit 7 654321 bit 0 read: tmrl7 tmrl6 tmrl5 tmrl4 tmrl3 tmrl2 tmrl1 tmrl0 write: reset: 11111100 = unimplemented figure 8-2. timer registers (tmrh/tmrl) acrh $001a bit 7 654321 bit 0 read: acrh7 acrh6 acrh5 acrh4 acrh3 acrh2 acrh1 acrh0 write: reset: 11111111 = unimplemented acrl $001b bit 7 654321 bit 0 read: acrl7 acrl6 acrl5 acrl4 acrl3 acrl2 acrl1 acrl0 write: reset: 11111100 = unimplemented figure 8-3. alternate counter registers (acrh/acrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required figure 8-4. state timing diagram for timer overflow the free-running counter is initialized to $fffc during reset. it is a read- only register. during power-on reset (por), the counter is initialized to $fffc and begins counting after the oscillator startup delay. because the counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262,144 ph2 clock cycles (524,288 oscillator cycles). when the free-running counter rolls over from $ffff to $0000, the timer overflow flag bit (tof) in register tsr is set. when counter rollover occurs, an interrupt also can be enabled by setting the timer overflow interrupt enable bit (toie) in register tcr. see figure 8-5 . figure 8-5. state timing diagram for timer reset $fffe $ffff $0000 $0001 $0002 16-bit free- running counter timer overflow flag (tof) ph2 clock note: the tof bit is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by reading the timer status register (tsr) during the high portion of the ph2 clock followed by reading the lsb of the counter register pair (tcrl). note: the counter and control registers are the only 16-bit timer registers affected by reset. ph2 clock internal reset 16-bit free- running counter reset (external or other) $fffc $fffd $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer 8.4 output compare the output compare function may be used to generate an output waveform and/or as an elapsed time indicator. all of the bits in the output compare register pair ocrh/ocrl are readable and writable and are not altered by the 16-bit timers control logic. reset does not affect the contents of these registers. if the output compare function is not utilized, its registers may be used for data storage. see figure 8-2 . the contents of the output compare registers are compared with the contents of the free-running counter once every four ph2 clock cycles. if a match is found, the output compare flag bit (ocf) is set and the output level bit (olvl) is clocked to the output latch. after each successful comparison, the values in the output compare registers and output level bit should be changed to control an output waveform or to establish a new elapsed timeout. an interrupt also can accompany a successful output compare if the output compare interrupt enable bit (ocie) is set. ocrh $0016 bit 7 654321 bit 0 read: ocrh7 ocrh6 ocrh5 ocrh4 ocrh3 ocrh2 ocrh1 ocrh0 write: reset: unaffected by reset = unimplemented ocrl $0017 bit 7 654321 bit 0 read: ocrl7 ocrl6 ocrl5 ocrl4 ocrl3 ocrl2 ocrl1 ocrl0 write: reset: unaffected by reset = unimplemented figure 8-6. output compare registers (ocrh/ocrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer output compare MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required after a cpu write cycle to the msb of the output compare register pair (ocrh), the output compare function is inhibited until the lsb (ocrl) is written. both bytes must be written if the msb is written. a write made only to the lsb will not inhibit the compare function. the free-running counter increments every four ph2 clock cycles. the minimum time required to update the output compare registers is a function of software rather than hardware. the output compare output level bit (olvl) will be clocked to its output latch regardless of the state of the output compare flag bit (ocf). a valid output compare must occur before the olvl bit is clocked to its output latch (tcmp). since neither the output compare flag (ocf) nor the output compare registers are affected by reset, care must be exercised when initializing the output compare function. this procedure is recommended: 1. block interrupts by setting the i bit in the condition code register (ccr). 2. write the msb of the output compare register pair (ocrh) to inhibit further compares until the lsb is written. 3. read the timer status register (tsr) to arm the output compare flag (ocf). 4. write the lsb of the output compare register pair (ocrl) to enable the output compare function and to clear its flag (and interrupt). 5. unblock interrupts by clearing the i bit in the ccr. this procedure prevents the output compare flag bit (ocf) from being set between the time it is read and the time the output compare registers are updated. a software example is shown in figure 8-7 and a state timing diagram is shown in figure 8-8 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer figure 8-7. output compare software initialization example figure 8-8. state timing diagram for output compare 9b . . b6 be b7 b6 bf . . 9a . . xx xx 16 13 17 . . sei . . lda ldx sta lda stx . . cli . . data h data l ocrh tsr ocrl . . block interrupts . . hi byte for compare lo byte for compare inhibit output compare arm ocf bit to clear ready for next com- pare . . notes: 1. the cpu write to the compare register may take place at any time, but a compare only occurs at timer state t01. thus, up to a four cycle difference may exist between the write to the compare register and the actual compare. 2. internal compare takes place during timer state t01. 3. the output compare ?ag bit (ocf) is set at timer state t11 which follows the comparison match ($ffed in this example). output compare flag and output pin 16-bit free- running counter compare register compare register latch ph2 clock $ffeb $ffec $ffed $ffee $ffef cpu writes $ffed $ffed (note 1) (note 2) (note 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer input capture MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required 8.5 input capture two 8-bit read-only registers (icrh and icrl) make up the 16-bit input capture. they are used to latch the value of the free-running counter after a defined transition is sensed by the input capture edge detector. (note that the input capture edge detector contains a schmitt trigger to improve noise immunity.) the edge that triggers the counter transfer is defined by the input edge bit (iedg) in register tcr. reset does not affect the contents of the input capture registers. see figure 8-2 . the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the ph2 clock preceding the external transition (see figure 8-10 ). this delay is required for internal synchronization. resolution is affected by the prescaler, allowing the free-running counter to increment once every four ph2 clock cycles. the contents of the free-running counter are transferred to the input capture registers on each proper signal transition regardless of the state of the input capture flag bit (icf) in register tsr. the input capture icrh $0014 bit 7 654321 bit 0 read: icrh7 icrh6 icrh5 icrh4 icrh3 icrh2 icrh1 icrh0 write: reset: unaffected by reset = unimplemented icrl $0015 bit 7 654321 bit 0 read: icrl7 icrl6 icrl5 icrl4 icrl3 icrl2 icrl1 icrl0 write: reset: unaffected by reset = unimplemented figure 8-9. input compare registers (icrh/icrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer registers always contain the free-running counter value that corresponds to the most recent input capture. after a read of the msb of the input capture register pair (icrh), counter transfers are inhibited until the lsb of the register pair (icrl) is also read. this characteristic forces the minimum pulse period attainable to be determined by the time required to execute an input capture software routine in an application. reading the lsb of the input capture register pair (icrl) does not inhibit transfer of the free-running counter. again, minimum pulse periods are ones which allow software to read the lsb of the register pair (icrl) and perform needed operations. there is no conflict between reading the lsb (icrl) and the free-running counter transfer, since they occur on opposite edges of the ph2 clock. figure 8-10. state timing diagram for input capture input capture flag input capture register 16-bit free- running counter tcap pin input capture latch ph2 clock note: although the input capture pin is sampled at the rate of ph2, the internal function is updated at the rate of ph4. $ffec $ffed $ffee $ffef $ffeb (see note) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer control register MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required 8.6 timer control register the timer control (tcr) and free-running counter (tmrh, tmrl, acrh, and acrl) registers are the only registers of the 16-bit timer affected by reset. the output compare port (tcmp) is forced low after reset and remains low until olvl is set and a valid output compare occurs. icie input capture interrupt enable bit 7, when set, enables input capture interrupts to the cpu. the interrupt will occur at the same time bit 7 (icf) in the tsr register is set. ocie output compare interrupt enable bit 6, when set, enables output compare interrupts to the cpu. the interrupt will occur at the same time bit 6 (ocf) in the tsr register is set. toie timer overflow interrupt enable bit 5, when set, enables timer overflow (rollover) interrupts to the cpu. the interrupt will occur at the same time bit 5 (tof) in the tsr register is set. iedg input capture edge select bit 1 selects which edge of the input capture signal will trigger a transfer of the contents of the free-running counter registers to the input capture registers. clearing this bit will select the falling edge; setting it selects the rising edge. olvl output compare output level select bit 0 selects the output level (high or low) that is clocked into the output compare output latch at the next successful output compare. $0012 bit 7 654321 bit 0 read: icie ocie toie 000 iedg olvl write: reset: 000000u0 u = unaffected figure 8-11. timer control register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer 8.7 timer status register reading the timer status register (tsr) satisfies the first condition required to clear status flags and interrupts. the only remaining step is to read (or write) the register associated with the active status flag (and/or interrupt). this method does not present any problems for input capture or output compare functions. however, a problem can occur when using a timer interrupt function and reading the free-running counter at random times to measure an elapsed time. if the proper precautions are not designed into the application software, a timer interrupt flag (tof) could unintentionally be cleared if: 1. the tsr is read when bit 5 (tof) is set. 2. the lsb of the free-running counter is read, but not for the purpose of servicing the flag or interrupt. the alternate counter registers (acrh and acrl) contain the same values as the timer registers (tmrh and tmrl). registers acrh and acrl can be read at any time without affecting the timer overflow flag (tof) or interrupt. icf input capture flag bit 7 is set when the edge specified by iedg in register tcr has been sensed by the input capture edge detector fed by pin tcap. this flag and the input capture interrupt can be cleared by reading register tsr followed by reading the lsb of the input capture register pair (icrl). $0013 bit 7 654321 bit 0 read: icf ocf tof 00000 write: reset: u u u 00000 u = unaffected figure 8-12. timer status register (tsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16-bit timer timer operation during wait mode MC68HC05P1A rev. 3.0 general release specification 16-bit timer non-disclosure agreement required ocf output compare flag bit 6 is set when the contents of the output compare registers match the contents of the free-running counter. this flag and the output compare interrupt can be cleared by reading register tsr followed by writing the lsb of the output compare register pair (ocrl). tof timer overflow flag bit 5 is set by a rollover of the free-running counter from $ffff to $0000. this flag and the timer overflow interrupt can be cleared by reading register tsr followed by reading the lsb of the timer register pair (tmrl). 8.8 timer operation during wait mode during wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the mcu out of wait mode. 8.9 timer operation during stop mode when the mcu enters stop mode, the free-running counter stops counting (the ph2 clock is stopped). it remains at that particular count value until stop mode is exited by applying a low signal to the irq pin, at which time the counter resumes from its stopped value as if nothing had happened. if stop mode is exited via an external reset (logic low applied to the reset pin), the counter is forced to $fffc. if a valid input capture edge occurs at the tcap pin during stop mode, the input capture detect circuitry will be armed. this action does not set any flags or wake up the mcu, but when the mcu does wake up, there will be an active input capture flag (and data) from the first valid edge. if stop mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required 16-bit timer general release specification MC68HC05P1A rev. 3.0 16-bit timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required general release specification MC68HC05P1A section 9. instruction set 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . .82 9.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .83 9.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . .84 9.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . .86 9.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 9.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set 9.2 introduction the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 9.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set addressing modes MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required 9.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 9.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 9.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 9.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set 9.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 9.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000C$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 9.3.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the freescale assembler determines the shortest form of indexed addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required 9.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 9.4 instruction types the mcu instructions fall into five categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set 9.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 9-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required 9.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value. table 9-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set 9.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required table 9-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set 9.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 9-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction types MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required 9.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 9-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set 9.5 instruction set summary table 9-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction set summary MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (a) x ? ( x) = $ff C (x) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set instruction set summary MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required instruction set general release specification MC68HC05P1A rev. 3.0 instruction set ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
instruction set opcode map MC68HC05P1A rev. 3.0 general release specification instruction set non-disclosure agreement required 9.6 opcode map see table 9-7 on page 94. tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?ag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?ag z zero ?ag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?ag set or cleared n any bit not affected table 9-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general release specification MC68HC05P1A rev. 3.0 instruction set instruction set table 9-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification electrical specifications non-disclosure agreement required general release specification MC68HC05P1A section 10. electrical specifications 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.4 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 10.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 10.7 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . .98 10.8 3.3 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . .99 10.9 5.0 volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 10.10 3.3 volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 10.2 introduction this section contains the mcu electrical specifications and timing information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations general release specification MC68HC05P1A rev. 3.0 electrical specifications 10.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd note: this device is not guaranteed to operate properly at the maximum ratings. refer to 10.7 5.0 volt dc electrical characteristics and 10.8 3.3 volt dc electrical characteristics for guaranteed operating conditions. 10.4 operating range rating symbol value unit supply voltage v dd C0.3 to + 7.0 v input voltage v in v ss C0.3 to v dd 0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg C65 to + 150 c characteristic symbol value unit operating temperature range MC68HC05P1A (standard) MC68HC05P1A (extended) MC68HC05P1A (v) t a t l to t h 0 to +70 C40 to +85 C40 to +105 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications thermal characteristics MC68HC05P1A rev. 3.0 general release specification electrical specifications non-disclosure agreement required 10.5 thermal characteristics 10.6 power considerations the average chip-junction temperature, t j, can be obtained in c from: t j = t a + (p d q ja ) (1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd watts (chip internal power) p i/o = power dissipation on input and output pins (user-determined) for most applications, p i/o ? p int and can be neglected. the following is an approximate relationship between p d and t j (neglecting p i/o ): p d = k + (t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d (t a + 273 c) + q ja (p d ) 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d at equilibrium for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . characteristic symbol value unit thermal resistance pdip soic q ja 56 71 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations general release specification MC68HC05P1A rev. 3.0 electrical specifications 10.7 5.0 volt dc electrical characteristics characteristic symbol min typ max unit output voltage i load 2 10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage (i load = C0.8 ma) pa0Cpa7, pc2Cpc7, pb7Cpb5, tcmp, pd5 (i load = C5.0 ma) pc0Cpc1 v oh v dd C0.8 v dd C0.8 0.4 0.4 v output low voltage (i load = C1.6 ma) pa0Cpa7, pb5Cpb7,pc2Cpc7, pd5, tcmp (i load = 20 ma) pc0Cpc1 v ol 0.4 0.4 v input high voltage pa0Cpa7, pb5Cpb7, pc0Cpc7, pd5, tcap/pd7, irq, reset, osc1 v ih 0.7 v dd v dd v input low voltage pa0Cpa7, pb5Cpb7, pc0Cpc7, pd5, tcap/pd7, irq, reset, osc1 v il v ss 0.2 v dd v supply current run (note 3) wait (note 4) stop (note 5) 25 c 0 c to +70 c (standard) C40 c to +85 c (extended) C40 c to +105 c (v) i dd 3.5 1.8 1 2 4 6 5 3.5 15 20 30 50 ma ma m a m a m a m a i/o ports hi-z leakage current pa0Cpa7, pb5Cpb7, pc0Cpc7, pd5 i il 10 m a input pullup current pa0Cpa7 i il 51030 m a input current reset, irq, osc1, pd5, pd7/tcap i in 1 m a capacitance pa7Cpa0, pb5Cpb0 (input or output) reset, irq, osc1, osc2 c out c in 12 8 pf notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 c to +125 c, unless otherwise noted 2. all values shown reflect average measurements at midpoint of voltage range at 25 c. 3. run (operating) i dd and wait i dd measured using external square wave clock source (f osc = 4.2 mhz), all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 4. wait i dd : only timer system active. wait, stop i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd C0.2 v. wait i dd is affected linearly by the osc2 capacitance. 5. stop i dd measured with osc1 = v ss . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications 3.3 volt dc electrical characteristics MC68HC05P1A rev. 3.0 general release specification electrical specifications non-disclosure agreement required 10.8 3.3 volt dc electrical characteristics characteristic symbol min typ max unit output voltage i load 10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage (i load = C0.2 ma) pa0Cpa7, pb5Cpb7, pc2Cpc7, pd5, tcmp (i load = C1.5 ma) pc0Cpc1 v oh v dd C0.3 v dd C0.3 v output low voltage (i load = 0.4 ma) pa0Cpa7, pb5Cpb7, pc2Cpc7, pd5, tcmp (i load = 6.0 ma) pc0Cpc1 v ol 0.3 0.3 v input high voltage pa0Cpa7, pb5Cpb7, pc0Cpc7, pd5, tcap/pd7, irq, reset, osc1 v ih 0.7 v dd v dd v input low voltage pa0Cpa7, pb5Cpb7, pc0Cpc7, pd5, tcap/pd7, irq, reset, osc1 v il v ss 0.2 v dd v supply current run (note 3) wait (note 4) stop (note 5) 25 c 0 c to +70 c (standard) C40 c to +85 c (extended) C40 c to +105 c (v) i dd 1.0 0.5 0.5 1 2 5 2.5 1.4 10 15 20 40 ma ma m a m a m a m a i/o ports hi-z leakage current pa0Cpa7, pb5Cpb7, pc0Cpc7, pd5, tcap/pd7 i il 10 m a i/o pullup current pa0Cpa7 i il 510 m a input current reset, irq, osc1 i in 1 m a capacitance ports (as input or output) reset, irq c out c in 12 8 pf input pullup current (pullup device on) pa7Cpa0 i in 1320 m a notes: 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = C40 c to +125 c, unless otherwise noted 2. all values shown reflect average measurements at midpoint of voltage range at 25 c. 3. run (operating) i dd and wait i dd measured using external square wave clock source (f osc = 2.1 mhz), all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 4. wait i dd : only timer system active. wait, stop i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd C0.2 v. wait i dd is affected linearly by the osc2 capacitance. 5. stop i dd measured with osc1 = v ss . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations general release specification MC68HC05P1A rev. 3.0 electrical specifications figure 10-1. pa0Cpa7, pb5Cpb7, pc2Cpc5, pd5, and tcmp typical high-side driver characteristics figure 10-2. pa0Cpa7, pc2Cpc5, pb0Cpb5, pd5, and tcmp typical low-side driver characteristics notes: 1. at v dd = 5.0 v, devices are specified and tested for (v dd C v oh ) 800 mv @ i ol = C0.8 ma. 2. at v dd = 3.3 v, devices are specified and tested for (v dd C v oh ) 300 mv @ i ol = C0.2 ma. 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 - 1.0 ma - 2.0 ma - 3.0 ma - 4.0 ma - 5.0 ma v dd = 5.0 v i oh v dd C v oh 85 c 25 c nominal processing - 40 c 25 c nominal processing 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 - 1.0 ma - 2.0 ma - 3.0 ma - 4.0 ma - 5.0 ma v dd = 3.3 v i oh v dd C v oh 85 c - 40 c see note 1 see note 2 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10.0 ma v dd = 5.0 v i ol v ol 85 c - 40 c 25 c nominal processing see note 1 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10.0 ma v dd = 3.3 v i ol v ol 85 c - 4 0 c 25 c nominal processing see note 2 notes: 1. at v dd = 5.0 v, devices are specified and tested for v ol 400 mv @ i ol = 1.6 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 300 mv @ i ol = 0.4 ma. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications 3.3 volt dc electrical characteristics MC68HC05P1A rev. 3.0 general release specification electrical specifications non-disclosure agreement required figure 10-3. pc0Cpc1 typical high-side driver characteristics figure 10-4. pc0Cpc1 typical low-side driver characteristics notes: 1. at v dd = 5.0 v, devices are specified and tested for (v dd C v oh ) 800 mv @ i ol = C5.0 ma. 2. at v dd = 3.3 v, devices are specified and tested for (v dd C v oh ) 300 mv @ i ol = C1.5 ma. 25 c nominal processing 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 - 0.5 ma - 1.0 ma - 1.5 ma v dd = 3.3 v i oh v dd C v oh 85 c - 40 c see note 2 800 mv 700 mv 600 mv 500 mv 400 mv 300 mv 200 mv 100 mv 0 0 - 1.0 ma - 2.0 ma - 3.0 ma - 4.0 ma - 5.0 ma v dd = 5.0 v i oh v dd C v oh 85 c 25 c nominal processing - 40 c see note 1 notes: 1. at v dd = 5.0 v, devices are specified and tested for v ol 400 mv @ i ol = 20 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 300 mv @ i ol = 6.0 ma. 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 5.0 ma 10.0 ma 20.0 ma v dd = 5.0 v i ol v ol 85 c - 40 c 25 c nominal processing 400 mv 350 mv 300 mv 250 mv 200 mv 150 mv 100 mv 50 mv 0 0 2.0 ma 4.0 ma 6.0 ma 8.0 ma 10.0 ma v dd = 3.3 v i ol v ol 85 c 25 c nominal processing see note 2 see note 1 - 40 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations general release specification MC68HC05P1A rev. 3.0 electrical specifications figure 10-5. typical operating i dd (25 c) figure 10-6. typical wait mode i dd (25 c) 3.0 v 1000 m a 500 m a 4500 m a 4000 m a 3500 m a 1500 m a 0 0 0.5 mhz 1.0 mhz 1.5 mhz 2.0 mhz 1.8 v 3.6 v 4.5 v supply current (i dd ) internal operating frequency (f op ) 3000 m a 2500 m a 2000 m a 5.5 v 3000 m a 2500 m a 2000 m a 1500 m a 1000 m a 500 m a 0 0 0.5 mhz 1.0 mhz 1.5 mhz 2.0 mhz 3.0 v 4.5 v 3.6 v 5.5 v supply current (i dd ) internal operating frequency (f op ) 1.8 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications 5.0 volt control timing MC68HC05P1A rev. 3.0 general release specification electrical specifications non-disclosure agreement required 10.9 5.0 volt control timing characteristic symbol min max unit frequency of operation crystal option external clock option f osc dc 4.2 4.2 mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 2.1 2.1 mhz cycle time t cyc 476 ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 125 ns interrupt pulse period t ilil note 2 t cyc osc1 pulse width t oh , t ol 200 ns notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 c to +125 c, unless otherwise noted 2. the minimum period, t ilil , should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations general release specification MC68HC05P1A rev. 3.0 electrical specifications 10.10 3.3 volt control timing characteristic symbol min max unit frequency of operation crystal/ceramic resonator (note 2) rc oscillator external clock option f osc dc 2.0 2.0 2.0 mhz internal operating frequency (f osc ? 2) crystal/ceramic oscillator rc oscillator external clock f op dc 2.1 2.1 2.1 mhz cycle time (2 ? f osc )t cyc 1000 ns reset pulse width low (edge-triggered) t rl 1.5 t cyc time resolution (note 3) t resl 4.0 t cyc irq interrupt pulse width low (edge-triggered) t ilih 250 ns irq interrupt pulse period t ilil note 4 t cyc pa3Cpa0 interrupt pulse width high (edge-triggered) t ihil 250 t cyc pa3Cpa0 interrupt pulse period t ihih note 4 t cyc osc1 pulse width t oh , t ol 400 ns notes: 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = C40 c to +125 c, unless otherwise noted 2. use only at-cut crystals. 3. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 4. the minimum period, t ilil or t ihih , should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical specifications 3.3 volt control timing MC68HC05P1A rev. 3.0 general release specification electrical specifications non-disclosure agreement required pch pcl osc1 2 reset internal processor internal address bus 1 1ffe 1fff v dd v dd threshold (1-2 v typical) 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new pc 1fff notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the ph2 clock following the rising edge of reset initiates the reset sequence. note 3 new new op code pcl pch new pc new pc op code new pc clock 1 figure 10-7. power-on reset and external reset timing diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required electrical speci?cations general release specification MC68HC05P1A rev. 3.0 electrical specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification mechanical specifications non-disclosure agreement required general release specification MC68HC05P1A section 11. mechanical specifications 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.3 dual in-line package (case 710). . . . . . . . . . . . . . . . . . . . . .107 11.4 small outline integrated circuit (case 751f) . . . . . . . . . . . . .108 11.2 introduction this section gives the dimensions of the dual in-line package (dip) and the small outline integrated circuit (soic) package. 11.3 dual in-line package (case 710)

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non-disclosure agreement required mechanical speci?cations general release specification MC68HC05P1A rev. 3.0 mechanical specifications 11.4 small outline integrated circuit (case 751f)

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$" !" ! " !" # !" !! $ ! $" ! ! -a- -b- 114 15 28 -t- c m j -t- k 26x g 28x d 14x p r x 45 ? ! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification ordering information non-disclosure agreement required general release specification MC68HC05P1A section 12. ordering information 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .110 12.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . .112 12.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.2 introduction this section contains instructions for ordering custom-masked rom mcus. 12.3 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a freescale representative. submit these items when ordering mcus: ? a current mcu ordering form that is completely filled out (contact your freescale sales office for assistance.) ? a copy of the customer specification if the customer specification deviates from the freescale specification for the mcu ? customers application program on one of the media listed in 12.4 application program media f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required ordering information general release specification MC68HC05P1A rev. 3.0 ordering information the current mcu ordering form is also available through the freescale freeware bulletin board service (bbs). the telephone number is (512) 891-free. after making the connection, type bbs in lower-case letters. then press the return key to start the bbs software. 12.4 application program media please deliver the application program to freescale in one of the following media: ? macintosh 1 3 1/2-inch diskette (double-sided 800 k or double-sided high-density 1.4 m) ? ms-dos 2 or pc-dos tm 3 3 1/2-inch diskette (double-sided 720 k or double-sided high-density 1.44 m) ? ms-dos or pc-dos tm 5 1/4-inch diskette (double-sided double- density 360 k or double-sided high-density 1.2 m) use positive logic for data and addresses. when submitting the application program on a diskette, clearly label the diskette with this information: ? customer name ? customer part number ? project or product name ? file name of object code ? date ? name of operating system that formatted diskette ? formatted capacity of diskette on diskettes, the application program must be in motorolas s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ordering information rom program verification MC68HC05P1A rev. 3.0 general release specification ordering information non-disclosure agreement required note: begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank. refer to the current mcu ordering form for additional requirements. freescale may request pattern re-submission if non-user areas contain any non-zero code. if the memory map has two user rom areas with the same address, then write the two areas in separate files on the diskette. label the diskette with both file names. in addition to the object code, a file containing the source code can be included. freescale keeps this code confidential and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the file name of the source code. 12.5 rom program verification the primary use for the on-chip rom is to hold the customers application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. freescale inputs the customers application program code into a computer program that generates a listing verify file. the listing verify file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contain non-user rom code, such as self-check code. freescale sends the customer a computer printout of the listing verify file along with a listing verify form. to aid the customer in checking the listing verify file, freescale will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to freescale. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required ordering information general release specification MC68HC05P1A rev. 3.0 ordering information 12.6 rom verification units (rvus) after receiving the signed listing verify form, freescale manufactures a custom photographic mask. the mask contains the customers application program and is used to process silicon wafers. the application program cannot be changed after the manufacture of the mask begins. freescale then produces 10 mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customers user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualification or production. rvus are not guaranteed by freescale quality assurance. 12.7 mc order numbers table 12-1 shows the mc order numbers for the available package types. table 12-1. mc order numbers package type temperature mc order number 28-pin plastic dual in-line package (dip) 0 c to +70 c MC68HC05P1Ap 28-pin small outline integrated circuit (soic) 0 c to +70 c MC68HC05P1Adw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification mc68hcl05p1a non-disclosure agreement required general release specification MC68HC05P1A appendix a. mc68hcl05p1a a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 a.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .114 a.4 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 a.2 introduction this appendix introduces the mc68hcl05p1a, a low-power version of the MC68HC05P1A. all of the information in this document applies to the mc68hcl05p1a with the exceptions given in this appendix. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mc68hcl05p1a general release specification MC68HC05P1A rev. 3.0 mc68hcl05p1a a.3 dc electrical characteristics the data in 10.7 5.0 volt dc electrical characteristics and 10.8 3.3 volt dc electrical characteristics applies to the mc68hcl05p1a with the exceptions given in table a-1 , table a-2 , and table a-3 . table a-1. low-power output voltage (v dd = 1.8C2.4 vdc) characteristic symbol min typ max unit output high voltage (i load = C0.1 ma) pa0Cpa7, pb5Cpb7, pc2Cpc7, pd5, tcmp v oh v dd C0.3 v output low voltage (i load = 0.2 ma) pa0Cpa3, pb5Cpb7, pc2Cpc7, pd5, tcmp v ol 0.3 v table a-2. low-power output voltage (v dd = 2.5C3.6 vdc) characteristic symbol min typ max unit output high voltage (i load = C0.2 ma) pa0Cpa7, pb5Cpb7, pc2Cpc7, pd5, tcmp v oh v dd C0.3 v output low voltage (i load = 0.4 ma) pa0Cpa3, pb5Cpb7, pc2Cpc7, pd5, tcmp v ol 0.3 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hcl05p1a MC68HC05P1A rev. 3.0 general release specification mc68hcl05p1a non-disclosure agreement required table a-3. low-power supply current characteristic symbol min typ (1) max unit supply current (v dd = 4.5C5.5 vdc, f op = 2.1 mhz) run (note 2) wait (note 3) stop (note 4) 25 c 0 c to +70 c (standard) i dd 3.0 1.6 0.5 2.0 4.25 2.25 15 25 ma ma m a m a supply current (v dd = 2.5C3.6 vdc, f op = 1.0 mhz) run (note 2) wait (note 3) stop (note 4) 25 c 0 c to +70 c (standard) i dd 1.0 0.7 0.2 2.0 1.6 1.0 5.0 10.0 ma ma m a m a supply current (v dd = 2.5-3.6 vdc, f op = 500 khz) run (note 2) wait (note 3) stop (note 4) 25 c 0 c to +70 c (standard) i dd 600 350 0.2 2.0 800 500 5.0 10.0 m a supply current (v dd = 1.8-2.4 vdc, f op = 500 khz) run (note 2) wait (note 3) stop (note 4) 25 c 0 c to +70 c (standard) i dd 300 200 0.1 2.0 600 400 2 5 m a notes: 1. typical values reflect average measurements at midpoint of voltage range at 25 c. 2. run (operating) i dd and wait i dd measured using external square wave clock source with all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 3. wait i dd measured using external square wave clock source with all inputs 0.2 v from rail, no dc loads, less than 50 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. v il = 0.2 v, v ih = v dd C0.2 v. osc2 capacitance linearly affects wait i dd . 4. stop i dd measured with osc1 = v ss . all ports configured as inputs, v il = 0.2 v, v ih = v dd C0.2 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mc68hcl05p1a general release specification MC68HC05P1A rev. 3.0 mc68hcl05p1a figure a-1. maximum run mode i dd versus internal clock frequency figure a-2. maximum wait mode i dd versus internal clock frequency 0 internal clock frequency (mhz) run i dd (ma) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v dd = 2.5 to 3.6 v v dd = 1.8 to 2.4 v 0 internal clock frequency (mhz) wait i dd ( m a) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 v dd = 2.5 to 3.6 v v dd = 1.8 to 2.4 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hcl05p1a MC68HC05P1A rev. 3.0 general release specification mc68hcl05p1a non-disclosure agreement required a.4 mc ordering information table a-4 provides ordering information for available package types. table a-4. mc order numbers package type temperature mc order number 28-pin plastic dual in-line package (dip) 0 c to +70 c mc68hcl05p1ap 28-pin small outline integrated circuit (soic) 0 c to +70 c mc68hcl05p1adw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mc68hcl05p1a general release specification MC68HC05P1A rev. 3.0 mc68hcl05p1a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05P1A rev. 3.0 general release specification mc68hsc05p1a non-disclosure agreement required general release specification MC68HC05P1A appendix b. mc68hsc05p1a b.1 contents b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 b.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .120 b.4 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 b.5 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 b.2 introduction this appendix introduces the mc68hsc05p1a, a high-speed version of the MC68HC05P1A. all of the information in this document applies to the mc68hcsc05p1a with the exceptions given in this appendix. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mc68hsc05p1a general release specification MC68HC05P1A rev. 3.0 mc68hsc05p1a b.3 dc electrical characteristics the data in 10.7 5.0 volt dc electrical characteristics and 10.8 3.3 volt dc electrical characteristics applies to the mc68hsc05p1a with the exceptions given in table b-1 . table b-1. high-speed supply current characteristic symbol min typ (note 1) max unit supply current (v dd = 4.5C5.5 vdc, f op = 4.0 mhz) run (note 3) wait (note 4) stop (note 5) i dd 6.0 3.5 2.0 7.0 3.5 20 ma ma m a supply current (v dd = 3.0C3.6 vdc, f op = 2.1 mhz) rum (note 3) wait (note 4) stop (note 5) i dd 2.5 1.3 2.0 3.5 2.5 10 ma ma m a notes: 1. t a = 0 c to 70 c 2. typical values at midpoint of voltage range, 25 c only. 3. run (operating) i dd and wait i dd measured using external square wave clock source with all inputs 0.2 v from rail; no dc loads, less than 50 pf on all outputs, c l = 20 pf on osc2. 4. wait i dd measured using external square wave clock source with all inputs 0.2 v from rail, no dc loads, less than 50 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. v il = 0.2 v, v ih = v dd C0.2 v. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 = v ss . all ports configured as inputs, v il = 0.2 v, v ih = v dd C0.2 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hsc05p1a MC68HC05P1A rev. 3.0 general release specification mc68hsc05p1a non-disclosure agreement required b.4 control timing the data in 10.9 5.0 volt control timing and 10.10 3.3 volt control timing applies to the mc68hsc05p1a with the exceptions given in table b-2 and table b-3 . table b-2. high-speed control timing (v dd = 5.0 vdc 10%) characteristic symbol min max unit oscillator frequency crystal option external clock option f osc dc 8.0 8.0 mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 4.0 4.0 mhz internal clock cycle time t cyc 250 ns input capture pulse width t th , t tl 63 ns interrupt pulse width low (edge-triggered) t ilih 63 ns osc1 pulse width t oh , t ol 45 ns table b-3. high-speed control timing (v dd = 3.3 vdc 10%) characteristic symbol min max unit oscillator frequency crystal option external clock option f osc dc 4.2 4.2 mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 2.1 2.1 mhz internal clock cycle time t cyc 480 ns input capture pulse width t th , t tl 125 ns interrupt pulse width low (edge-triggered) t ilih 125 ns osc1 pulse width t oh , t ol 90 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required mc68hsc05p1a general release specification MC68HC05P1A rev. 3.0 mc68hsc05p1a b.5 mc ordering information table b-4 provides ordering information for available package types. table b-4. mc order numbers package type temperature mc order number 28-pin plastic dual in-line package (dip) 0 c to +70 c mc68hsc05p1ap 28-pin small outline integrated circuit (soic) 0 c to +70 c mc68hsc05p1adw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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